ASML Develops Hybrid Bonding Equipment

According to semiconductor research firm SemiAnalysis on October 15, photolithography equipment manufacturer ASML has not officially announced hybrid bonding equipment, but patents and the company's roadmap indicate that it is under development. The article suggests that ASML may first launch more complex chip-to-wafer hybrid bonding tools, viewing it as an extension of vertical integration. The patents show that the system operates on a track, with each chip placed in an independent carrier, sequentially completing inspection, cleaning, plasma activation, morphology inspection, leveling, coarse alignment, position adjustment, and fine alignment before entering the bonding station, ultimately placed by the carrier and suction cup. The track's repeat accuracy is about 10 microns, which is lower than the approximately 50 nanometers required for bonding. ASML submitted 27 bonding patent families from December 2022 to November 2024, most of which are aimed at chip-to-wafer. The Elec reported in March that ASML has begun hybrid bonding architecture design with Prodrive Technologies and VDL ETG. The article mentions that wafer-to-wafer hybrid bonding has been used for image sensors and 3D NAND, while chip-to-wafer is currently only used for mass production of logic chips, including the hybrid bonding V-Cache shipped by AMD since 2022 and TSMC's SoIC. The current spacing of SoIC is about 6 microns, with a target of reaching 4.5 microns by around 2029. Besi is currently the only supplier with chip-to-wafer mass production tools, with related logic business mainly concentrated in TSMC and Intel.

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